A processor typically employs one or more clock signals to synchronize logic operations at modules of the processor, thereby preventing errors such as setup errors, race conditions, and the like. A typical processor employs different clock signals for different portions of the processor, wherein each processor portion is referred to as a clock domain. By employing different clock domains, the processor operates the different portions at different frequencies, and also operates the different portions relatively independently with respect to timing of the logic operations. For example, the processor can synchronize the different clock domains with clock signals of different frequencies, thereby improving processing efficiency. Further, the processor can provide different clock signals to different clock domains without synchronizing the different clock signals, thereby simplifying clock management and signal routing at the processor. However, when data is communicated across clock domains of the processor, meta-stability errors can arise. These errors can be ameliorated by including a meta-stability circuit, such set of flip-flops, between the clock domains to effectuate the data transfer. However, such meta-stability circuits can add latency, as well as require extra circuitry (such as extra entries of a buffer) to address control signal delays. The errors can also be reduced by employing a first-in first-out buffer (FIFO) to transfer data across clock domains, but conventional FIFOs can introduce errors in the data transfer when the clock frequency for one of the time domains is altered, either because of a voltage droop or because of a change in power mode of one or more of the clock domains.